An alternative low resistance MOL technology with electroplated rhodium as contact plugs for 32nm CMOS and beyond

This paper addresses a critical CMOS challenge of increasing parasitic resistance by introducing electroplated rhodium (Rh) as an alternative middle-of-line (MOL) metallurgy to replace the conventional CVD tungsten (W) processes for lower contact resistance and better extendibility to 32nm technology and beyond. Electroplating of Rh is shown to have similar to Cu superconformal filling capability, allowing us to successfully fill high aspect ratio vias (40nm × 240nm). Plating of 300 mm wafers with 60nm × 290nm vias was demonstrated using CVD or ALD ruthenium (Ru) as the seed layer. An annealing process was developed to obtain a thin Rh film resistivity of 6.5 &3x003BC;Ω-cm, which is 1.5 to 3X lower than the resistivity of CVD W films. Since Rh is stable in Si environment, when compared to a fast diffusing Cu, a very thin Ti/Ru layer can be implemented. Therefore we propose to use PVD Ti/ALD Ru/electroplated Rh as the alternative MOL metallurgy. With this simple liner/seed/fill stack, the overall MOL resistance is calculated to be 2x lower than the overall MOL resistance of the conventional W stacks, and slightly lower than Cu fill stacks. In addition, the ability to use a thinner liner layer than that used for Cu-base fill process, provides a greater potential for extendibility of Rh fill into future CMOS MOL generations.