An Efficient HW/SW Implementation of the H.263 Video Coder in FPGA

In this paper, we present an efficient HW/SW codesign architecture for H.263 video coder and its FPGA implementation. Each module of the coder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portion include the discrete cosine transform (DCT) and inverse DCT (IDCT). Remaining parts were realized in software with NIOS II softcore processor. This paper also introduces efficient design methods for HW and SW modules. In hardware, an efficient architecture for the 2-D DCT and 2-D IDCT is suggested to reduce the chip size. Software optimization technique is also explored by using the fast block-matching algorithm for motion estimation (ME). The whole design are described in VHDL language and implemented in stratix EP2S60 FPGA. Finally, the coder has been tested on the altera NIOS II development board.