A Low-Power Highly Linear CMOS Transconductance Topology

A new technique for realizing highly low-power linear transconductances is presented. The technique is based on using floating transistors in the input stage of the transconductor acting as source followers along with a degeneration resistor. Using floating transistors guarantees that the input signal is replicated almost perfect to the resistor terminals and constitute a close-to-ideal transconductance. There could be many ways of realizing the technique considering the required linearity, the power consumption and the frequency response parameters. An example embodiment of the technique was studied followed by circuit level simulations carried out using 0.18 um CMOS technology. Simulation results show that for an input signal of 1.8 Vpp (peak to peak) and power supply of 1.8 v, the Total Harmonic Distortion (THD) was less that 103 dB (<10
^-3
%) with 200 muA current consumption for a normalized output which shows the high linearity of the transconductance.