Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders

In this communication, the delay variability due to supply variations is investigated for two important Full Adder topologies. An analytical model of the delay sensitivity to supply variations is developed for the static and the Complementary Pass Gate Logic (CPL) logic style. The model is very simple and independent of the adopted technology, thus it allows for identifying the main parameters which define the delay variability due to supply variations, as well as deriving design considerations. From the model, several interesting properties are derived, such as the importance of the input rise/fall time variations and the effect of the voltage and technology scaling. The model is validated by means of SPICE simulations with a 0.18-μm and a 0.35-μm technology.