A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers

This paper presents a new low-power and compact digital active pixel sensor (APS) for hybrid CMOS imagers. The proposed self-biased topology includes built-in dark current and input capacitance compensation, mixed integration, A/D conversion and a purely digital I/O interface, all at pixel level. Furthermore, full FPN compensation and AGC capabilities are also supplied by digitally pre-programming the individual sensitivity of each APS during the read-out phase without any speed reduction. In this sense, experimental results are reported for a 100
μ
m×100
μ
m complete APS circuit in standard 0.35
μ
m CMOS 2-polySi 4-metal technology for IR applications.