A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation

A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21ps
_rms
jitter for 2
³¹
-1 PRBS, 9.5mV
_pp
input sensitivity with BER <10
^-12
, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm
²
.