Process Algebraic Approach to SystemVerilog

We develop a process algebraic framework, called process algebraic framework for IEEE 1800trade SystemVerilog (PAFSV), for formal specification and analysis of IEEE 1800trade SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a labelled transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800trade SystemVerilog. This paper serves as an introduction of PAFSV to architects, engineers and researchers from the electronic design community.