Reliability Studies on Non Planar DRAM Cell Transistor

We have experimentally analyzed the leakage mechanism and device degradations caused by the F-N and hot carrier stresses for the recently developed DRAM cell transistors having deeply recessed channels. We have found the important difference of the leakage mechanism between S-Fin and RCAT, which have each structural benefit in the characteristics of leakage current, so we can suggest the guide lines for device structures simultaneously having the each merit in both structures.