Drain Extended NMOS High Current Behavior and ESD Protection Strategy for HV Applications in Sub-100nm CMOS Technologies

In this work the high current behavior of drain-extended nMOS transistors (DEnMOS) built in a state-of-the-art 65nm CMOS technology were investigated. It shown that a sufficient level of ESD robustness (I
_T2
~2mA/mum) can be achieved through substrate biasing. The concept will be exploited to build robust ESD protections