An Investigation of Chip-Level Hardware Support for Web Mining

In this work, we investigate the use of hardware at the chip level to support some fundamental Web mining operations. Both software and hardware versions of the same operators are implemented on field programmable gate arrays (FPGAs). The software versions are executed on a soft IP core on the same FPGA chip as the hardware implementation, ensuring their fair performance comparison. The hardware operators are structured hierarchically following the bottom-up and platform-based design strategies. These design approaches provide the opportunity to measure the performance of the respective hardware and software operators at various levels of abstraction. Our proof of concept investigation has shown that with the proper system-level design strategies, there is a tremendous potential in hardware support at the chip level for information retrieval and Web mining operations.