A Novel Multiplierless Hardware Implementation Method for Adaptive Filter Coefficients

Adaptive filter implementations require real-time conversion of coefficients to canonical signed digit (CSD) or similar representations to benefit from multiplierless techniques for implementing filters. Multiplierless approaches are used to reduce the hardware and increase the throughput. This paper introduces a novel hardware implementation method that converts two's complement numbers to their CSD representations using a fixed number of shift and logic operations. As a result, we can greatly reduce the power consumption and area requirements for hardware implementation of DSP algorithms in which coefficients are not known a priori. Because all CSD digits are produced simultaneously, the conversion speed and thus the throughput are improved when compared to overlap-and-scan techniques such as Booth's recoding.