Adaptive Bit-Reliability Mapping for LDPCCoded High-Order Modulation Systems

In this paper, an adaptive bit-reliability mapping is proposed for the bit-level Chase combining in LDPC-coded high-order modulation systems. Contrary to the previously known bit-reliability mapping that assigns the information (or parity) bits to more (or less) reliable bit positions, the proposed mapping flexibly assigns codeword bits to the bit positions of various reliabilities by considering the characteristics of code and protection levels. Compared with the symbol-level Chase combining and the constellation rearrangement bit mapping, the proposed mapping gives 0.7 - 1.3 dB and 0.1 - 1.0 dB performance gain at FER = 10
^-3
with no additional complexity, respectively. The adaptive bit-reliability mappings are derived for various environments and the validity of them is confirmed through simulation.