First Silicon Functional Validation and Debug of Multicore Microprocessors

Microprocessor designs are increasingly moving towards multiple cores on a single die. Validating memory consistency, coherency, ordering, and atomicity is crucial. X86 microprocessors are prevalent at most levels of computing. Thus, new x86 microprocessors undergo extensive compatibility testing. Being a high volume product, the economic and logistical repercussions of a functional deficiency escaping into the production cycle and beyond are humbling. The first silicon functional validation and debug of multicore microprocessors are constrained by design complexity, compatibility with existing hardware and software, and time-to-market pressures. This paper describes microprocessor debug features and their use in debugging functional failures. An encompassing overview of the microprocessor's first silicon validation is presented. Emphasis is put on validation and debug of multicore microprocessors targeting multinode systems. This paper presents a novel method to validate and debug intra-node and inter-node communication traffic. This paper also develops an analysis to determine optimal on die debug resources. Finally, data from an 8-node system is presented to demonstrate the extent of intrusiveness of a coherent and noncoherent traffic debug feature