Event Driven Data Processing Architecture

This paper describes a data processing architecture where events and time are in focus. This differs from traditional von Neumann and data flow architectures. New instruction codes are defined and special circuitry is introduced to express and execute event and time operations. This results in reconfigurable software controlled functionality together with real-time performance comparable to dedicated VLSI solutions. The architecture is demonstrated in a real-time radar jammer application. The architecture is promising also for applications as routers and network processors. A prototype system on silicon (SoC), complete with signal memory, instruction memory, four processing units in parallel and interfaces for digitized signals and host computer, is fabricated in 0.35 mum standard CMOS. Time events of signal data on two simultaneous 8-bit links can be programmed with a time resolution of one clock period. Measurements verified correct function and performance above 400 MHz clock frequency at 3.3 Volt supply. Power consumption is 3.6-Watt @320 MHz