A 0.6-V, 6.8-μW Embedded SRAM for Ultra-low Power SoC

A novel embedded SRAM is proposed with features of high reliability and low power consumption. The critical control signals are made in correspondence to clock-duty cycle for high reliability. A hybrid precharge scheme is adopted for low power consumption. Additionally, an asymmetric read-write scheme is useful in a slow-but-steady write situation such as a control SoC for BSN (body sensor network). The fabricated 128-kb embedded SRAM consumes 117-μW at the worst case and 6.8-μW at normal write operation in a 0.6-V supply voltage.