A 1/f-Noise Reduction Architecture for an Operational Amplifier in a 0.13 μm Standard digital CMOS technology

We present new circuit architecture for the 1/f noise reduction in a CMOS Miller operational amplifier. Compared to a reference circuit, the 1/f noise reduction of 7 dB is achieved for a CMOS Miller operational amplifier implemented in a 0.13 μm 1.5 V standard CMOS technology. This architecture successfully reduces the 1/f noise and is applicable to a continuous signal processing analog IC's.