Low-Power High-Speed 180-nm CMOS Clock Drivers

The power dissipation (P
_T
) and delay time (t
_dT
) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were fabricated using 0.18-mum CMOS technology. The first and second stages of the driver consisted of a single inverter and m inverters, respectively, and the register array stage was constructed with N delay flip-flops (D-FFs). A single inverter in the second stage drove N/m D-FFs where N was fixed at 40 and m varied from 1 to 40. Minimum P
_T
and t
_dT
were 251 muW and 0.640 ns, respectively and were both obtained at an m of 8. These values were 48.6% and 29.4% of maximum P
_T
and t
_dT
respectively. Simulated and measured results agreed well with these SPICE simulated results.