Maximization of Good Chips Per Wafer by Optimization of Memory Redundancy

In the optimization of the number of good chips per wafer, yield is obviously one key factor. It plays the major role in the manufacturing phase, as at this time circuit design and chip area cannot be modified. In the design phase, however, chip area as the second factor defining good chips per wafer can still be influenced. If there are no strong relationships between yield and chip area, both can be optimized independently. In some cases, however, there are such strong relationships, and an optimum of yield gain versus area growth has to be found. Maybe the most important example where strong relationships between area and yield have to be considered is the estimation of optimum memory redundancy. In this paper, we will review and discuss relationships between yield and area and present methods for optimization of good chips per wafer, with special focus on the optimization of memory redundancy