Removing ill-structured arcs in Hierarchical and Concurrent State Diagrams

This paper starts presenting a methodology for embedded systems co-design where statecharts play the role of specification formalism. The system model is expressed using a statechart model, which is a kind of hierarchical and concurrent state diagram, and the methodology relies on the decomposition of the system model into a set of parallel components. The system model is edited using a UML-2.0 compliant graphical editor, and the tool described in this paper produces an intermediary representation of the components using XML (after model partitioning), amenable to feed automatic code generation tools, allowing production of VHDL-code, C-code, or SystemC-code. The paper presents a set of arc lifting mechanisms to be applied to an ill-structured hierarchical and concurrent state diagram in order to obtain a well-structured model, which, according with methodology's requirements, is a requisite for removing hierarchical structures in the model and allow partitioning of the model into a set of concurrent components.