Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems

In this paper we propose a methodology that takes into account bit-width to optimize area and power consumption of hardware architectures provided by high level synthesis tools. The methodology is based on a bit-width analysis using information that comes from the designer. This bit-width information is propagated through a graph which models the application. The resulting annotated graph enables datapath structure optimizations for high level synthesis without increasing dramatically its processing time (complexity: O(n)). The methodology was applied to several signal and image processing applications. Our results demonstrate the effectiveness of the approach. It can be also applied in a more general design context for sizing the data of an application knowing the input data formats and their potential correlation.