On Accelerating Soft-Error Detection by Targeted Pattern Generation

Soft error due to ionizing radiation is emerging as a major concern for future technologies. The measurement unit for failures due to soft errors is called failure-in-time (FIT) that represents the number of failures encountered per billion hours of device operation. FIT rate measurement is time consuming and calls for accelerated testing. There are multiple ways to accelerate soft error rate (SER) testing. Acceleration by increasing radiation and lowering supply voltage has been reported. In this paper we propose increasing the rate of failure due to soft error by intelligent pattern selection. The proposed approach is based on the fact that all circuit nodes are not equally susceptible to faults due to soft error. We propose a pattern selection technique which specifically targets the most vulnerable nodes in the circuit and construct a test set to maximize failure rate due to soft error. The solution is based on a combination of ILP and fault simulation techniques. The test set thus derived can be applied repeatedly to accelerate the soft error rate testing. Results based on ISCAS circuits show that it is possible to achieve 10times acceleration by this technique