Hardware Implementation of 64B/66B Encoder/Decoder for 10-Gigabit Ethernet

The encoding and decoding rules of 64B/66B and inherent characteristic among 64B/66B codes are studied in this paper. A hardware implementation of 64B/66B encoder/decoder is introduced, which combines the advantages of lookup-table and logic analysis methods with low resource consumption, High speed and high reliability. The algorithm of encoding and decoding is described with Verilog HDL, and was simulated and synthesized with high performance FPGA of Xilinx. So the hardware circuit is realized to validate the feasibility of this method. The design of different high speed 64B/66B encoding and decoding module or IC is easily fulfilled with it.