A 1.2 billion operations per second video signal processing chip

Presents a new VLSI processor for image compression and machine vision which combines principles of multi-pipeline and array processing. The device is designed to function as a 2D vector accelerator, as is required for many image coding/processing/vision tasks. The device (DIP chip) is not specific to any one image algorithm, and can be regarded as a general purpose processor. It has variable bit accuracy, variable kernel size and a high input/output bandwidth (greater than 1.2 billion bits per second), and is designed to perform a wide variety of mathematical functions, especially 2D accumulation.<
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