A general purpose, single chip video signal processing (VSP) architecture for image processing, coding and computer vision

The paper describes the architecture of a novel, internally multiprocessing, single chip VSP. The limitations of extended DSP architectures and conventional array processors are discussed in the context of the functional domains of image processing, coding and computer vision. Integration of a novel array-based processing core, together with a RISC processor and intelligent memory management processor provide flexibility. The core architecture is an enhanced array processor whose key features are: 2 bit data path, dual processor mesh connected array planes and combined SIMD/systolic functionality. The core is optimised for 2D windowed operations, particularly 2D MAC and transforms. The device is expected to operate at 80 MHz on low voltage silicon and deliver in excess of 3 G Op s/sup -1/ across a range of target applications.<
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