Modelling of low noise InP based HEMTs

A device model for both high frequency small signal and noise behaviour of InP-HEMTs, depending on both gate and drain source voltage has been developed. It could be shown, that the optimum gate bias for low noise is, when the drain current is reduced to one third the value required for maximum gain. However, it was found that the optimum gate source voltage is frequency dependent. Regarding the source drain voltage, lowest noise is observed at the start of the saturation region, i.e. V
_ds
, = 0.6 V. Since the model includes not only the intrinsic channel and induced gate noise sources but also Johnson noise of the extrinsic elements, it can be used to model scaling effects of the noise behaviour. It could be shown, that lowest noise is observed for a single-finger HEMT with a gate width of 40 μm. Multi-finger layouts are preferable for gate widths above 70 μm.