Hardware Support for Fast Reconfigurability in Progress Arrays

Massively parallel computers are implemented by means of modules at different packaging levels. This paper discusses a hierarchical node clustering scheme (HNC) for packaging a class of reconfigurable processor arrays called Polymorphic Processor Array (PPA) which uses circuit-switchingbased routers at each node to deliver a different topology at every instruction. The PPA family suffers from an unknown signal delay between arbitrary two nodes connected by the circuited-switched paths. This either forces the hardware clock to compromise to the worst signal delay or makes the software dependent on the system size. The use of the HNC scheme allows to obtain communication speed-up and automatic control, at the compiler level, over signal propagation delay.