Accurate System Voltage and Timing Margin Simulation in CDR Based High Speed Designs

Accurate analysis of system timing and voltage margin at a target bit error rate across process, voltage, and temperature variations is required for high volume production of high speed systems. This in turn requires a statistical simulation framework to model the effectiveness of advanced signaling techniques such as transmitter equalization and receiver decision feedback. Furthermore, for data and telecommunication networking serial links, one must also carefully model the clock-data recovery circuits (CDR) and understand their impact on system voltage and timing margin. In this paper, we first present a stochastic simulation framework and describe a modeling methodology for CDR circuits. We then compare the simulation results based on CDR modeling to a simple method, which uses a quadrature sampling based timing recovery model. Finally, we correlate the simulation results to lab measurements to validate the proposed approach