Functional Test Generation for Finite State Machines

In this paper, a pure functional test generation method for finite state machines (FSM) is proposed. The method is solely based on state transition diagram (STD) description of FSMs. It guarantees full coverage of stuck-at faults in a two-level implementation of the sum-of-product forms of the next state logic and output logic synthesized from the STD. For simplification the test generation process and reducing the test length, the state flip-flops are made observable. Experiments show the efficiency of the method