Testability Analysis of Digital Design Verification

A new method of testability analysis of digital design verification is presented. The method describes substantial graph-schemes that give possibility to simplify the verification task and to generate test synthesis and and/or to improve faults covering for the given inputs. The topological analysis of an oriented graph and further modification by separation of operating modes (test and functional) of a digital device is the base of the proposed technique. The main goal of the presented algorithm is improvement of testability and simplification of the verification task