New Floating Gate Self-Aligning Technology for Multilevel NOR Flash Memory

This paper describes the key technology to realize a scaled multilevel NOR flash memory with an improved gate oxide integrity. It is found that a thin poly-Si employed in STI formation is a good buffer layer to prevent the oxide local thinning at STI corners of both cell and peripheral areas. Using the poly-Si as a sacrificial-layer during tunnel oxide growth, a 65nm NOR flash memory with a cell size of 0.039 mum
²
has been developed and achieved the multilevel cell (MLC) operation. Also, an improved post-cycled retention characteristics has been obtained