Sampling Receive Equalizer with Bit-Rate Flexible Operation up to 10 Gbit/s

A receive equalizer IC implemented in 0.13 mum standard CMOS technology is presented. The equalizer filter works with sampled analog signals within a half-rate architecture. Due to its discrete-time nature, the circuit operates continuously on bit rates ranging from 0.5 Gbit/s to 10 Gbit/s. The equalizer core consists of a 3-tap finite-impulse-response filter and a subsequent decision-feedback filter with first and second post cursor feedback taps. Up to 24 dB channel loss at the Nyquist frequency can be compensated. The reception of a 2
³¹
-1 PRBS binary data stream transmitted over a 90 cm long trace on FR4 with 10 Gbit/s and over a 173 cm long trace with 7 Gbit/s with a BER < 10
^-12
and receive-only equalization is presented. The power consumption of the equalizer core is 21 mW and the core area is 60 mum times 56 mum