A Low Power CMOS Time-to-Digital Converter Based on Duty Cycle Controllable Pulse Stretcher

A low cost and low power CMOS time-to-digital converter (TDC) with 50ps time resolution is proposed in this paper. Two parallel time interpolators are used to improve the resolution by pulse stretching. In addition to conventional current ratio and capacitor ratio, the duty cycle of the discharging clock is also incorporated to adjust the stretch factor to reduce the power consumption and chip area dramatically. The interpolators are based on analog dual-slope conversion. The time resolution is measured as 50ps and the INL error is within plusmn1.1 LSB for input range up to 250 ns. The voltage drift is 3.8ps/V or equivalently plusmn3.5% over 3.0~4.0 V supply voltage range. The measured resolution is within 49.8ps to 52.7ps for six packaged chips and the chip size is merely 0.5 mm times 0.45 mm as fabricated in the TSMC 0.35-mum CMOS digital process. The power consumption is 0.75mW, enormously reduced from hundreds of milliwatts of the predecessors, at 100k samples/s and the measurement rate can achieve as high as 150k samples/s