A Low-power BitStream Controller for H.264/AVC Baseline Decoding

In this paper, we present the design and VLSI implementation of a low-power bitstream controller for H.264/AVC baseline profile decoding. It is comprised of bitstream parsing and three dedicated decoders for intra-prediction mode, inter-motion vector and boundary strength. Various low-power design techniques, such as statistic-based data driven decoding, hierarchical FSM decomposition, nonuniform LUT partition favoring smaller tables, module-wise clock gating are employed. Due to a clever architecture design, the proposed work is capable of decoding realtime QCIF of 30 fps at a required operating frequency as low as 1MHz or even slower. A prototype chip, fabricated in a 0.18μm CMOS process, has an area of 3.6mm2 with 47k gate counts and dissipates 113μW of power on a 1.8V supply.