Low Power LVDS Driver Used in ADC Systems

A low power LVDS driver embedded in ADC system is presented. A new current mirror circuit is used to guarantee the matching between the top and bottom current sources. The current flowing through the termination resistors can be controlled by an off-chip resistor. By combining the design concepts of prior arts, the driver is fabricated in a 0.18mum 1.8V CMOS process. The simulated results show that it guarantees 100 Msps data rate of high-speed pipelined ADC with the consumption of 12.78 mw/bit