Latch-Based Clocking for Portable Low-Power Audio Applications

Two DSP algorithms for hearing aids have been integrated on silicon in a 0.18 mum CMOS process. Various level-sensitive two-phase clocking schemes have been evaluated in terms of energy efficiency. Actual measurements have confirmed energy savings of 64% over a recently published clock-gated single-edge-triggered one-phase implementation. Most of these improvements can be attributed to the thinning out of the clock tree made possible by the relaxed slew and skew constraints of level-sensitive clocking schemes