Leakage Power Reduction for CMOS Combinational Circuits

In this paper, the problem of leakage power reduction by means of input vector control was studied, and a platform for CMOS combinational circuit leakage power reduction was developed. Genetic algorithm is used for searching minimum leakage vector with circuit status difference as fitness function. Experimental results indicate that the method can achieve satisfied leakage power reduction, and the run time is reasonable. This method has no requirement for Spice simulation and independent from target technology