Electrical properties and temperature behavior of strained-Si N-MOSFETs

Strained-Si n-MOSFET transistors were fabricated on strained Si/uniform relaxed Si
_0.9
Ge
_0.1
/relaxed graded SiGe/Si substrate using reduced pressure chemical vapor deposition (RPCVD) technique. The transistors show a significant mobility enhancement of ~50% compared to control Si n-MOSFET mobilities at low vertical field and at room temperature. The drain current is increased by ~40% for long channel devices. The temperature behavior including the variation of the inversion layer mobility, the threshold voltage shifts and the reduction of saturated drain current, has been investigated for operating temperatures ranging from room temperature to 70degC compared with strained-Si and Si control n-MOSFET transistors. It was found that the electron mobility has the largest enhancement around room temperature