A 16/spl times/16-bit static CMOS wave-pipelined multiplier

A 16/spl times/16-bit wave-pipelined multiplier was designed using static CMOS. Wave pipelining is achieved by applying new data to the circuit faster than the propagation delay. The circuit has been fabricated in a 1.0 /spl mu/m CMOS process and tested at 330-350 MHz, which is about 4 times faster than the maximum clock frequency without pipelining.<
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