A Design Methodology for MOS Current-Mode Logic Frequency Dividers

In this work, a methodology for the design of MOS current-mode logic frequency dividers is presented. A mix of hand calculations and circuit simulations is used to relate the power consumption and the frequency of operation. Each latch in the dividers is sized separately in order to minimize the overall power consumption. Furthermore, the effect on the power consumption of circuit parameters such as output swing and voltage gain of the input differential pair is analyzed in detail. The methodology has been applied to dividers by two and dividers by three with 50% output duty cycle