A floorplanner driven by structural and timing constraints

This paper presents a novel layout model and floorplanning tool particularly suitable for taking into account user defined layout constraints on specific sets of modules and specific locations. The user defined layout constraints can be the setting of any common topological property associated with a group of specific modules such as the neighboring property for example. Or the use of any topological regularities in a design such as regular bus structure or the use of the structural property such as the bit-sliceable or non bit-sliceable feature of a module set, or their similar shape. The exploitation of these structural information helps in producing more compact layout especially for datapath oriented architectures. Moreover, in addition to the area and total wiring length, the critical path delay is systematically minimized through a global cost function. The potential candidates for the critical path computation can be specifically defined by the user. The core of the optimization process is based on simulated annealing.<>