Test Vector Ordering For Power Reduction During Transmission of Compressed Test Patterns To Embedded System-On-Chip

This paper considers the problem of test-bus power reduction in system-on-chip testing. It has been seen that while the cores are fitted with P1500 wrapper, transitions occurring in the bypass registers can be comparable to those in the scan chain. Unlike bus encoding the proposed solution using test vector reordering does not use any extra hardware. It neither affects the compression ratio nor test application time. Experimental results on ISCAS89 benchmark circuits show up to 75% saving in flip count occurring in test bus in a dictionary based test data compression