A FPGA-based Architecture for Block Matching Motion Estimation Algorithm

A FPGA-based architecture to achieve a real time processing of full-search block matching motion estimation algorithm, is described. Although many ASICs for motion estimation have been developed, either the chip complexity is too high or the optimal accuracy was not achieved. Based on the regular parallel design a real-time FPGA chip is designed and it has been implemented using 16- processing elements to meet the real time requirement. The design can achieve clock frequency up to 120 MHz. Its performance has been compared with other architectures reported in the literature and the results are encouraging.