An Area-Efficient Reed-Solomon Decoder for HDTV Channel Demodulation

In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for Reed-Solomon (RS) decoding. The proposed architecture is exploited based on the features of vector operations of the decoding algorithm. By pipelining and folding, the proposed architecture can improve the reuse rate of the main computation unit, reduce the hardware complexity and delete the redundant circuits. Synthesized by the Cadence Ambittrade tool using the TSMC 0.25 mum standard cell library, the implemented RS decoder consists of about 27,000 gates, which is about 39% smaller than the same kind of conventional ones. It has been integrated in a channel demodulation chip for high-definition television (HDTV) and has been tested successfully in practice