Error control on in-building power line communication channels

Forward error correction (FEC) coding is evaluated for enhancement of reliability and information throughput on power line communication channels. Rate one-half self-orthogonal convolutional codes with majority logic decoding are considered. A (2, 1, 6) code with bit interleaving to degree 7 was particularly effective, and was implemented as a VLSI microelectronic chip. Extensive bit error rate and packet error rate tests on in-building power line links showed coding gains in excess of 15 dB at 10/sup -3/ channel error rates. Tests were conducted at data rates from 1.2 to 28.8 kb/s.<
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