A Novel Strain Method for Enhancement of 90-nm Node and Beyond FUSI-Gated CMOS Performance

A novel strain engineering technique for a fully silicided (FUSI) metal gate called contact etch stop layer (CESL)-enveloped FUSI was developed for the first time. A CESL was deposited prior to the FUSI RTP2 (the second rapid thermal process of FUSI gate formation) to confine the Ni
_x
Si FUSI. Then, the phase transfer and volume change of the enveloped FUSI after RTP2 induced a tensile stress to enhance I
_ON
. For example, 500 degC RTP2 induced 1-GPa tensile stress on a blanket wafer test and gained 10% improvement in the I
_ON
of the n-channel metal-oxide-semiconductor. The mechanisms of the improvement were also nicely supported by transmission-electron-microscope cross-section analysis, X-ray-diffraction spectrum, and simulation confirmation data