Supply noise and CMOS synchronization errors

The effects of supply disturbances on synchronization failures in CMOS latches are examined. In contrast to prior work, supply noise is shown to increase a synchronizer's metastability error rate. Buffering the synchronizer to reduce these errors is shown to have little effect on the noise immunity. Measured results are presented from a test setup with a 2-/spl mu/m CMOS test chip to verify the findings.<
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