A 3.1 to 10.6 GHz 100 Mb/s Pulse-Based Ultra-Wideband Radio Receiver Chipset

A complete 3.1-10.6 GHz ultra-wide band receiver using 500 MHz-wide sub-banded binary phase shift keyed (BPSK) pulses has been specified, designed and integrated as a three chip and planar antenna solution. The system includes a custom designed 3.1-10.6 GHz planar antenna, direct-conversion RF front-end, 500 MS/s analog to digital converters, and a parallelized digital back-end for signal detection and demodulation. A 100 Mb/s wireless link has been established with this chipset. A bit-error-rate (BER) of 10
^-3
was recorded at -80 dBm at a rate of 100 Mb/s for properly acquired packets in the lowest frequency band. Bit-scaling of the ADC from 1 to 5 bits reveals a 4 dB improvement in the link budget