Negative gate bias instability in polycrystalline silicon TFT's

Degradation of the device characteristics of poly-Si TFT's are seen following negative gate bias stress at elevated temperatures. The degradation has two components, One component is the trapping of holes in the gate oxide; this is a similar phenomenon to the so called 'negative bias instability' seen in mono-Si MOSFETs. The other component is state formation and removal in the poly-Si bulk, or at the poly-Si-SiO/sub 2/ interface, and this is similar to that seen in /spl alpha/Si:H TFT's. The states formed are not the same as those produced by hot carrier stressing.<
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