An asynchronous communication protocol for internode connections in a scalable processor array

The authors describe an asynchronous communication protocol and an interface circuit which are used for internode communication in a reconfigurable DSP array. The communication protocol is derived from methods applied in digital communication, where the received data is synchronized to the local clock. Data is written into a FIFO that works as an elastic storage. For simple synchronization of the incoming data, a write signal runs in parallel with data and the implementation is based on synchronous logic primitives available in standard gate arrays. The maximum communication rate is the half of the system clock and depends only on the metastable recovery time of the applied devices, rather than the interconnection delay between the modules. An implementation example demonstrates a 22 Mbit/s asynchronous communication link, applied between multiple standard 1 /spl mu/ gate arrays.<
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