A Computer-Oriented Factoring Algorithm for NOR Logic Design

Because transistor NOR gates allow only a liitmed number of inputs, NOR equations must be factored before they can be implemented. An easily programmed algorithm is developed which rapidly generates a subset of factors, selects optimum factors, and indicates a realization for the factored equation based on the relation A ↓ B ↓ C ↓ D = [(A ↓ B) ↓] ↓ C ↓ D. A method for preventing excessive fan-out is also presented.